Flash memory is a type of non-volatile electronic storage medium that can be electronically erased and reprogrammed, thus well suited as a rewritable, compact data-storage medium used in electronic systems, in computer systems, and especially in mobile devices.
NAND flash memory is one of the main types of flash memory that uses floating-gate transistors connected serially in a NAND gate fashion. The NAND flash memory is widely used in computer systems, digital cameras, portable music players, USB flash drives, memory cards, and SmartMedia™ cards. Particularly in computer systems and persistent data storage systems, it is increasingly common that magnetic disk-based data storage media are being replaced by solid state disks that utilize NAND flash memories as these solid state disks maintain certain advantages over magnetic disk-based data storage media in that they have less power consumption, better physical shock resistance and electromagnetic compatibility characteristics, smaller physical size, and lower weight.
NAND flash memories come in different capacities and electronic architectures depending on the manufacture, model, and technology used. For example, memory banks in a NAND flash memory device are arranged into blocks with sizes including but not limited to 256K, 512K, 1M, or 2M bytes. Each block is further organized into pages. The number of pages can be 32, 64, 128, or more with each page having a possible size of 256, 512, 1K, 2K, 4K, 8K bytes or more. Other technical variations arise in other attributes such as block type, address cycles, and size of spare memory space.
In general the data storage operations of NAND flash memories comprise three basic operations: page read, page program (or equivalent to write), and block erase. Before a page can be programmed or re-programmed, a block erase of the block containing the page must be performed first. The speeds of the operations are asymmetrical. A page read is much faster than a page program or block erase. In addition, memory cells of NAND flash memories have limited lifespan. A memory cell will wear out after certain number of erase-cycles. Typically, a single-level-cell (SLC) has a life of 100,000 erase-cycles, and a multi-level-cell (MLC) has a life of 3,000 to 10,000 erase-cycles. Thus, various data storage operation schemes have been developed to minimize the block erase operations and spread the block erase operations evenly to all blocks.
In the art, execute in place (XIP) is a method of executing a program directly from a long-term storage rather than copying the program into a RAM first. A NAND flash memory is a typical non-XIP memory. A non-XIP memory does not provide an interface directly connectable with a central processing unit (CPU). Furthermore, the non-XIP memory is not directly connectable with a memory in a host, such as RAM, for data transfer because of the aforementioned differences between a RAM and the NAND flash memory or the non-XIP memory in general. A flash-memory controller is required to facilitate data transfer between the non-XIP memory and a host memory or a CPU.
FIG. 1 is a schematic diagram showing a typical arrangement of transferring data between a host memory and one or more flash memory modules through direct memory access (DMA). Consider, for example, that a command of writing data from the host memory to a flash memory module is received by a CPU. The CPU instructs a DMA controller to transfer a page of data from the host memory to a data buffer that is coupled to the DMA controller and a flash-memory controller. After the page of data is transferred to the data buffer, the DMA controller may submit an interrupt to the CPU. Upon receiving the interrupt, the CPU is aware that the page of data in the data buffer is ready. Alternatively, the CPU may be informed by regularly polling the DMA controller. Then the CPU issues a program command, optionally prior to an erase command, to the flash-memory controller to write the page of data from the data buffer to the flash memory module. When the program command is done, the CPU is informed about its completion by the flash-memory controller sending an interrupt to the CPU or by the CPU regularly polling the flash-memory controller. The CPU then repeats the process of instructing the DMA to load another page to the data buffer followed by commanding the flash-memory controller to do a program operation until all the data are transferred. The process is almost the same in a read operation. Interrupt or polling is also needed in an erase operation. As the process is repeated many times, a high CPU load is resulted. Furthermore, it leads to low efficiency for the CPU in that a new flash-operation command can be issued only after completion of a previous command (both commands being for the same flash memory module).
There is a need in the art for a method to transfer data between a host memory and a flash memory module with reduced CPU load and/or increased CPU efficiency to achieve an improvement over the aforementioned typical arrangement.